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Control Register

X

B1

X

X

INT1

7

6

5

4

3

2

1

0

Interrupt

(ReadOnly)

Bits

ChannelSelectionBits

(Read/Write)

Channel0

Channel1

INT0

INT1

INT0

X

B0

Control Register Definition

Interrupt Handling

PCA9543A

WITH INTERRUPT LOGIC AND RESET

SCPS169 – SEPTEMBER 2007

Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9543A,

which is stored in the control register (see Figure 3). If multiple bytes are received by the PCA9543A, it saves the

Figure 3. Control Register

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see

Table 1). After the PCA9543A has been addressed, the control register is written. The two LSBs of the control

byte are used to determine which channel or channels are to be selected. When a channel is selected, the

lines are in a high state when the channel is made active, so that no false conditions are generated at the time of

connection. A stop condition must occur always right after the acknowledge cycle.

D7

D6

INT1

INT0

D3

D2

B1

B0

COMMAND

0

Channel 0 disabled

X

X

X

X

X

X

X

1

Channel 0 enabled

0

Channel 1 disabled

X

X

X

X

X

X

X

1

Channel 1 enabled

0

0

0

0

0

0

0

0

No channel selected; power-up/reset default state

(1)

Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.

The PCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (see

Table 2). When an interrupt is generated by any device, it is detected by the PCA9543A and the interrupt output

is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control

register.

Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the PCA9543A, respectively.

Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is

loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to

channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the

PCA9543A and read the contents of the control register to determine which channel contains the device

generating the interrupt. The master then can reconfigure the PCA9543A to select this channel, and locate the

device generating the interrupt and clear it.

It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to

ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required.

4

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Product Folder Link(s): PCA9543A