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P11C68-45DPBS Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc

Part # P11C68-45DPBS
Description  CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

P11C68-45DPBS Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc

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P10C68/P11C68
10
Standard
tNLQX
tNLNH
tGLNL
tWHNL
tELNL
tNLQZ
Alternative
tRECALL
tRC
Parameter
Recall cycle time
Recall initiation cycle time
Output enable set-up
Write enable set-up
Chip enable set-up
NE (bar) fall to output inactive
Units
µs
µs
ns
ns
ns
ns
Notes
19
20
Symbol
Min.
25
0
0
0
Max.
20
25
Min.
25
0
0
0
Max.
20
25
P10C68-45
P10C68-35
P10C68 RECALL CYCLE 1 : NE (BAR) CONTROLLED
(See note 16)
P10C68 RECALL CYCLE 3 : G (BAR) CONTROLLED
(See note 16)
Alternative
tRECALL
tRC
Parameter
Recall cycle time
Recall initiation cycle time
NE (bar) set-up
Write enable set-up
Chip enable set-up
Units
µs
ns
ns
ns
ns
Notes
19
20
Symbol
Min.
25
0
0
0
Max.
20
Min.
25
0
0
0
Max.
20
P10C68-45
P10C68-35
Standard
tGLQX2
tGLNH
tNLGL
tWHGL
tELGL
NOTES
19.
Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Address transitions may not occur on
any address pin during this time.
20.
Once tRC has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the RECALL cycle is completed automatically. Any
of NE (bar), G (bar) or E (bar) may be used to terminate the RECALL initiation cycle.
P10C68 RECALL CYCLE 2 : E (BAR) CONTROLLED
(See note 16)
Alternative
tRECALL
tRC
Parameter
Recall cycle time
Recall initiation cycle time
NE (bar) set-up
Output enable set-up
Write enable set-up
Units
µs
ns
ns
ns
ns
Notes
19
20
Symbol
Min.
25
0
0
0
Max.
20
Min.
25
0
0
0
Max.
20
P10C68-45
P10C68-35
Standard
tELQX2
tELNH
tNLEL
tGLEL
tWHEL


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