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TC74VCX16843FT Datasheet(PDF) 7 Page - Toshiba Semiconductor

Part # TC74VCX16843FT
Description  Low-Voltage 18-Bit D-Type Latch with 3.6-V Tolerant Inputs and Outputs
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC74VCX16843FT Datasheet(HTML) 7 Page - Toshiba Semiconductor

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TC74VCX16843FT
2007-10-19
7
AC Characteristics (Ta = −40 to 85°C, input: tr = tf = 2.0 ns, CL = 30 pF, RL = 500 Ω) (Note 1)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
1.8
1.5
7.4
2.5
± 0.2
0.8
3.7
Propagation delay time
(D-Q)
tpLH
tpHL
Figure 1, Figure 2
3.3
± 0.3
0.6
3.0
ns
1.8
1.5
8.8
2.5
± 0.2
0.8
4.4
Propagation delay time
(LE-Q)
tpLH
tpHL
Figure 1, Figure 2
3.3
± 0.3
0.6
3.5
ns
1.8
1.5
9.8
2.5
± 0.2
0.8
5.6
Propagation delay time
( PR -Q)
tpLH
Figure 1, Figure 3
3.3
± 0.3
0.6
4.0
ns
1.8
1.5
9.2
2.5
± 0.2
0.8
4.6
Propagation delay time
( CLR -Q)
tpHL
Figure 1, Figure 3
3.3
± 0.3
0.6
3.7
ns
1.8
1.5
9.8
2.5
± 0.2
0.8
4.9
3-state output enable time
tpZL
tpZH
Figure 1, Figure 4
3.3
± 0.3
0.6
3.8
ns
1.8
1.5
7.6
2.5
± 0.2
0.8
4.2
3-state output disable time
tpLZ
tpHZ
Figure 1, Figure 4
3.3
± 0.3
0.6
3.7
ns
1.8
4.0
2.5
± 0.2
1.5
Minimum pulse width
(LE, PR ,
CLR )
tW (H)
tW (L)
Figure 1, Figure 2, Figure 3
3.3
± 0.3
1.5
ns
1.8
2.5
2.5
± 0.2
1.5
Minimum setup time
ts
Figure 1, Figure 2
3.3
± 0.3
1.5
ns
1.8
1.0
2.5
± 0.2
1.0
Minimum hold time
th
Figure 1, Figure 2
3.3
± 0.3
1.0
ns
1.8
4.0
2.5
± 0.2
3.0
Minimum removal time
trem
Figure 1, Figure 5
3.3
± 0.3
2.0
ns
1.8
0.5
2.5
± 0.2
0.5
Output to output skew
tosLH
tosHL
(Note 2)
3.3
± 0.3
0.5
ns
Note 1: For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
Note 2: Parameter guaranteed by design.
(tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)


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