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AX88772 Datasheet(PDF) 6 Page - ASIX Electronics Corporation

Part # AX88772
Description  USB to 10/100 Fast Ethernet/HomePNA Controller
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88772 Datasheet(HTML) 6 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
6
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
Input, 2.5V with 3.3V tolerant
B2
Bi-directional I/O, 2.5V with 3.3V tolerant
I3
Input, 3.3V
B5
Bi-directional I/O, 3.3V with 5V tolerant
I5
Input, 3.3V with 5V tolerant
PU
Internal Pull Up (75K)
O2
Output, 2.5V with 3.3V tolerant
PD
Internal Pull Down (75K)
O3
Output, 3.3V
P
Power Pin
O5
Output, 3.3V with 5V tolerant
S
Schmitt Trigger
B
Bi-directional I/O
Table 1: Pinout Description
Pin Name
Type
Pin No
Pin Description
USB Interface
DP
B
32
USB 2.0 data positive pin.
DM
B
31
USB 2.0 data negative pin.
DPRS
B
36
USB 1.1 data positive pin. Please connect to DP through a 39ohm
(+/-1%) serial resistor.
DMRS
B
35
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
VBUS
I5/PD/S
10
VBUS pin input. Please connect to USB bus power.
XIN12M
I3
26
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate. The recommended operating frequency
range is 12.000800Mhz ~12.004800Mhz.
XOUT12M
O3
27
12Mhz crystal or oscillator clock output.
RREF
I
30
For USB PHY’s internal biasing. Please connect to AGND through a
12.1Kohm (+/-1%) resistor.
RPU
I
34
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Interface
MDC
O2
121
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
MDIO
B2/PU
120
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
MDINT
I2/PU
117
Station Management Interrupt input.
MII Interface
RX_CLK
I2
104
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII interface.
RXD [3:0]
I2
110, 109,
108, 107
Receive Data. RXD [3:0] is driven synchronously with respect to
RX_CLK by PHY.
RX_DV
I2
105
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [3:0].
RX_ER
I2
106
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
COL
I2
116
Collision Detected. COL is driven high by PHY when the collision is
detected.


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