MT9171/72

Data Sheet

2

Zarlink Semiconductor Inc.

with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop

reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

22

24

28

11

2

22

3

Internal Bias Voltage output. Connect via 0.33

µF decoupling capacitor to V

33

4

Internal Reference Voltage output. Connect via 0.33

µF decoupling capacitor to

4,5,

6

4,5,

6

5,7,

8

MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the

various operating modes for a particular application. See Table 1 for the

operating modes.

77

9

RegC

Regulator Control output (Digital). A 512 kHz clock used for switch mode power

supplies. Unused in MAS/MOD mode and should be left open circuit.

89

10

F0/CLD

Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative

pulse input for the MASTER indicating the start of the active channel times of the

device. Output for the SLAVE indicating the start of the active channel times of

the device. Output in MOD mode providing a pulse indicating the start of the C-

channel.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

22

21

20

19

18

17

16

15

22 PIN PDIP

LOUT

VBias

VRef

MS2

MS1

MS0

RegC

F0/CLD

CDSTi/CDi

CDSTo/CDo

VSS

VDD

LIN

TEST

LOUT DIS

Precan

OSC1

OSC2

C4/TCK

F0o/RCK

DSTi/Di

DSTo/Do

28 PIN PLCC

5

6

7

8

9

10

11

25

24

23

22

21

20

19

•

NC

LOUT DIS

Precan

OSC1

OSC2

NC

C4/TCK

MS2

NC

MS1

MS0

RegC

F0/CLD

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

24

23

22

21

20

19

18

17

24 PIN SSOP

LOUT

VBias

VRef

MS2

MS1

MS0

RegC

F0/CLD

CDSTi/CDi

CDSTo/CDo

VSS

NC

VDD

LIN

TEST

LOUT DIS

Precan

OSC1

OSC2

C4/TCK

F0o/RCK

DSTi/Di

DSTo/Do

NC