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M36W0R6030B0ZAQE Datasheet(PDF) 8 Page - STMicroelectronics |
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M36W0R6030B0ZAQE Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 26 page M36W0R6030T0, M36W0R6030B0 8/26 FUNCTIONAL DESCRIPTION The Flash memory and SRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: EF for the Flash memory and E1S and E2S for the SRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read oper- ations on one of the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 4. Functional Block Diagram AI08536C E1S E2S GS WS DQ0-DQ15 VDDF A0-A18 A19-A21 8 Mbit SRAM GF UBS LBS WAITF 64 Mbit Flash Memory VDDS EF KF WF LF RPF WPF VPPF VDDQ VSS |
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