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MT9171AN Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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MT9171AN Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
1 / 28 page 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved. Features • Full duplex transmission over a single twisted pair • Selectable 80 or 160 kbit/s line rate • Adaptive echo cancellation • Up to 3 km (9171) and 4 km (9172) • ISDN compatible (2B+D) data format • Transparent modem capability • Frame synchronization and clock extraction • Zarlink ST-BUS compatible • Low power (typically 50 mW), single 5 V supply Applications • Digital subscriber lines • High speed data transmission over twisted wires • Digital PABX line cards and telephone sets • 80 or 160 kbit/s single chip modem Description The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem March 2006 Ordering Information MT9171/72AE 22 Pin PDIP Tubes MT9171/72AN 24 Pin SSOP Tubes MT9171/72AP 28 Pin PLCC Tubes MT9171/72APR 28 Pin PLCC Tape & Reel MT9171/72ANR 24 Pin SSOP Tape & Reel MT9171/72AE1 22 Pin PDIP* Tubes MT9171/72AP1 28 Pin PLCC* Tubes MT9171/72AN1 24 Pin SSOP* Tubes MT9171/72APR1 28 Pin PLCC* Tape & Reel MT9171/72ANR1 24 Pin SSOP* Tape & Reel *Pb Free Matte Tin -40 °C to +85°C ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet Figure 1 - Functional Block Diagram DSTi/Di CDSTi/ F0/CLD C4/TCK F0o/RCK MS0 MS1 MS2 RegC DSTo/Do CDSTo/ CDo Transmit Interface Prescrambler Scrambler Control Register Transmit/ Clock Receive Timing & Control Status Transmit Timing Master Clock Phase Locked Sync Detect Receive DPLL Receive Interface De- Prescrambler Descrambler Differentially Encoded Biphase Receiver Differentially Encoded Biphase Transmitter Transmit Filter & Line Driver Receive Filter -1 +2 MUX Address Echo Canceller Error Signal Echo Estimate VBias VDD VSS VBias VRef LOUT LOUT DIS Precan LIN OSC2 OSC1 — + ∑ CDi |
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