MT9171/72

Data Sheet

7

Zarlink Semiconductor Inc.

Figure 7 - CD Port (Modes 2,6)

Figure 8 - CD Port (Modes 1,5)

Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides

first order antialiasing for the received signal. Internal, partial cancellation of the near end signal may be disabled by

holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension

applications. The Precan pin features an internal pull-down which allows this pin to be left unconnected in

applications where this function is not required. The resultant signal passes through a receive filter to bandlimit and

equalize it. At this point, the echo estimate from the echo canceller is subtracted from the precancelled received

signal. This difference signal is then input to the echo canceller as an error signal and also squared up by a

comparator and passed to the biphase receiver. Within the echo canceller, the sign of this error signal is

determined. Depending on the sign, the echo estimate is either incremented or decremented and this new estimate

is stored back in RAM.

The timebase in both SLV and MAS modes (generated internally in SLV mode and externally in MAS mode) is

phase-locked to the received data stream. This phase-locked clock operates the Biphase Decoder, Descrambler

and Deprescrambler in MAS mode and the entire chip in SLV mode. The Biphase Decoder decodes the received

encoded bit stream resulting in the original NRZ data which is passed onto the Descrambler and Deprescrambler

where the data is restored to its original content by performing the reverse polynomials. The SYNC bits are

F0

C4

CDSTo

CDSTi

F0o

3.9

µsec

62.5

µsec

125

µsec

Channel Time 0

Channel Time 16

CLD

TCK

CDi

CDo