Part Name
         Description
NCP4331

 Synchronous Buck Controller for High Efficiency Post Regulation ( 23 Page)


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NCP4331
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ELECTRICAL CHARACTERISTICS (VCC = 20 V, VBST = 7 V, HB Grounded, TJ = 0°C to +125°C, unless otherwise specified)
Symbol
Unit
Max
Typ
Min
Rating
ERROR AMPLIFIER
Vref
Referenced Voltage Regulation @ Pin 7 Being Open
0
°C < TJ < 85°C
-40
°C < TJ < 125°C (Guaranteed by Test from 0°C < TJ < 125°C and
Extended to -40
°C by Design)
0.738
0.735
0.750
0.750
0.762
0.765
V
IBFB
Feedback Input Bias Current @ Vpin6 = Vref
-500
-250
0
nA
BW
Gain Bandwidth
-
4
-
MHz
GEA
Open Loop Voltage Gain
-
70
-
dB
EAout
-EAmax
-EAmin
Pin 5 (Compensation) Voltage
Vpin6 = 0 V
Vpin6 = 1 V
3.50
-
3.70
0.05
-
0.50
V
Isource-EA
Output Source Current @ Vpin6 = 0 V
40
65
90
mA
SOFT-START AND MAXIMUM DUTY-CYCLE LIMITATION (Dmax)
ISS
Source Current @ VSS = 0 V to 3.5 V
40
50
63
mA
VSS
Clamp Voltage
3.5
3.7
-
V
EAMIN
Error Amplifier Output @ Vpin5 = 0.5 V
-
0.05
0.5
V
EASS
Error Amplifier Output @ Vpin6 = 0 V and Vpin7 = 2 V
1.9
2.0
2.1
V
RAMP CONTROL
Iramp
Cramp Current Source @ Vramp = 0 V to 3.5 V
40
50
63
mA
VrampH
Cramp Ramp Clamp
3.5
3.7
-
V
VrampL
Low Voltage of the Ramp Saw-Tooth
-
-
100
mV
VrampON
Ramp Voltage Enabling the High-Side Driver:
@Vpin5 = 0.5 V
@ Vpin5 = 3.5 V (Min Highest EA Value)
@ Vpin5 = 2 V
2.30
-
0.80
2.50
-
1.00
2.65
0
1.20
V
QRESET
Current Charge Extracted During the RESET Pulse (Note 4)
5
-
-
nC
TRESET
Delay from SYNC Pin low to Reset Completion (a Falling Pulse Being
Applied to Pin 16)
-
200
350
ns
RRESET
Sink Resistance of Pin 8 during the Reset Time @ Ipin8 = 10 mA (This is
the Resistance of the Switch that Discharges the Cramp Capacitor during
the Reset Pulse - Capability of 5 nC Min)
-
15
25
W
SYNCHRONIZATION BLOCK
VSYNCH
Synchronization Comparator Threshold (Vpin9 Rising)
2.4
2.5
2.6
V
HSYNC
Synchronization Comparator Hysteresis
1.2
1.5
1.8
V
VCL-SYNC
Negative Clamp Voltage of the Synchronization Pin @ Ipin16 = 2 mA
-0.3
-
0
V
TSYNCwHS
Delay From SYNC Pin High to HS_DRV High
(A Rising PUlse Being Applied to Pin 16)
-
100
250
ns
UNDERVOLTAGE DETECTION (UVP)/SHUTDOWN
VUVPL
Comparator Threshold (Vpin4 Being Falling)
1.92
2.00
2.08
V
VUVPH
Comparator Threshold (Vpin4 Being Rising) (Note 5)
-
-
2.20
V
HUVP
Hysteresis of the UVP Comparator
-
40
-
mV
IUVP
UVP Current Source
15
25
30
mA
IBUVP
Bias Current
-
-
0.1
mA
3. The risetime is the time needed by the drive to go from 10% to 90% of the supply voltage. The fall time is the time required by the drive
to drop from 90% to 10% of its supply voltage. These times are not tested in production but only guaranteed by design.
4. Guaranteed by design. Tested through the RRESET parameter.
5. Guaranteed by characterization and design.
6. This delay is specified with the HB pin being grounded. In typical application where the HB node is pulsing, the delay is 70 ns typically
1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23 



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