Electronic Components Datasheet Search |
|
LTC1860 Datasheet(PDF) 10 Page - Linear Technology |
|
LTC1860 Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LTC2453 10 2453f Discarding a Conversion Result and Initiating a New Conversion It is possible to start a new conversion without reading the old result, as shown in Figure 7. Following a valid 7-bit address, a read request (R) bit, and a valid ACK, a STOP command will start a new conversion. PRESERVING THE CONVERTER ACCURACY The LTC2453 is designed to dramatically reduce the conver- sion result’s sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nev- ertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC – 0.5V may result in additional cur- rent leakage from the part. Driving VCC and GND In relation to the VCC and GND pins, the LTC2453 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1μF, high quality, ceramic capacitor in parallel with a 10μF ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1μF capacitor should be placed closest to the ADC package. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have three distinct connections: the SLEEP 7-BIT ADDRESS (0010100) SP R ACK READ DATA OUTPUT CONVERSION CONVERSION 2453 F05 Figure 5. The LTC2453 Coversion Sequence SLEEP SLEEP SP R ACK READ READ DATA OUTPUT CONVERSION CONVERSION 2453 F06 S RP ACK CONVERSION DATA OUTPUT 7-BIT ADDRESS (0010100) 7-BIT ADDRESS (0010100) Figure 6. Consecutive Reading at the Same Configuration Figure 7. Start a New Conversion without Reading Old Conversion Result SLEEP SP R ACK READ (OPTIONAL) DATA OUTPUT CONVERSION CONVERSION 2453 F07 7-BIT ADDRESS (0010100) APPLICATIONS INFORMATION |
Similar Part No. - LTC1860 |
|
Similar Description - LTC1860 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |