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LTC4223CDHD-1PBF Datasheet(PDF) 4 Page - Linear Technology

Part # LTC4223CDHD-1PBF
Description  Dual Supply Hot Swap Controller for Advanced Mezzanine Card
Download  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4223CDHD-1PBF Datasheet(HTML) 4 Page - Linear Technology

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LTC4223-1/LTC4223-2
4
422312f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ITMR(UP)
TIMER Pull-Up Current
VTIMER = 1V, Initial Timing Cycle
VTIMER = 0V, In AUX Fault Mode
VTIMER = 0V, In 12V Fault Mode
–7
–7
–140
–10
–10
–200
–13
–13
–260
μA
μA
μA
ITMR(DN)
TIMER Pull-Down Current
VTIMER = 2V, No Faults
VTIMER = 2V, In Reset Mode
1.3
2
2
8
2.6
16
μA
mA
Open Drain Outputs
VOL
Output Low Voltage (⎯F⎯A⎯U⎯L⎯T, ⎯1⎯2⎯P⎯G⎯O⎯O⎯D,
⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D)
IOL = 3mA
0.15
0.4
V
VOH
Output High Voltage (⎯F⎯A⎯U⎯L⎯T, ⎯1⎯2⎯P⎯G⎯O⎯O⎯D,
⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D)
(Note 5)
VCC – 1
V
IPU
Output Pin Pull-Up Current (⎯F⎯A⎯U⎯L⎯T,
⎯1⎯2⎯P⎯G⎯O⎯O⎯D, ⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D)
VPU = 1.5V
–6
–10
–14
μA
Logic Inputs
VIN(TH)
Logic Input Threshold (12ON, AUXON, ⎯E⎯N)
0.8
2
V
IIN(LEAK)
Input Leakage Current (12ON, AUXON)
VIN = VCC
±1
μA
RPU
⎯E⎯N Pin Pull-Up Resistance
60
100
140
Other Pin Functions
I12VSENSE
12VSENSE Pin Input Current
V12VSENSE = 12V
10
50
100
μA
I12VOUT
12VOUT Pin Input Current
Gate Drive On, V12VOUT = 12V
20
50
100
μA
ROUT(DIS)
OUT Pin Discharge Resistance
12VOUT
AUXOUT
Gate Drive Off
V12VOUT = 6V
VAUXVOUT = 2V
400
375
800
750
1600
1500
Ω
Ω
Propagation Delays
tCB
AUX Circuit Breaker Trip Delay
After Power Up
12
25
50
μs
tPHL(SENSE)
Sense Voltage, (12VIN – 12VSENSE)
High to 12VGATE Low
ΔVSENSE = 300mV, C12VGATE = 10nF
ΔVSENSE = 100mV, C12VGATE = 10nF
0.5
5
1
12
μs
μs
tPHH(AUXON)
AUXON High to AUXOUT High
15
30
μs
tPHH(12ON)
12ON High to 12VGATE High
30
60
μs
tRST(ON)
Input Low (12ON, AUXON) to ⎯F⎯A⎯U⎯L⎯T High
20
40
μs
tRST(VCC)
VCC Low to ⎯F⎯A⎯U⎯L⎯T High
80
150
μs
tPLL(UVLO)
12VIN Low to 12VGATE Low
612
18
μs
AUXIN Low to ⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D High
612
18
μs
tPHL(GATE)
⎯E⎯N High to 12VGATE Low
20
40
μs
tPLH(PG)
12VOUT Low to ⎯1⎯2⎯P⎯G⎯O⎯O⎯D High
20
40
μs
AUXOUT Low to ⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D High
20
40
μs
tP(12IMON)
Input Sense Voltage Step to 12IMON
Propagation Delay
ΔVSENSE = 100mV
26
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 3: An internal clamp limits the 12VGATE pin to a minimum of 4.5V
above 12VOUT. Driving this pin to voltages beyond the clamp may damage
the device.
Note 4: For the DFN package, the AUX switch on resistance, RDS(ON) limit
is guaranteed by correlation to wafer test measurements.
Note 5: The output pins ⎯F⎯A⎯U⎯L⎯T, ⎯1⎯2⎯P⎯G⎯O⎯O⎯D and ⎯A⎯U⎯X⎯P⎯G⎯O⎯O⎯D have an internal
pull-up to VCC of 10μA. However, an external pull-up resistor may be used
when faster rise time is required or for VOH voltages greater than VCC.
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C, VCC = 3.3V, VAUXIN = 3.3V, V12VIN =12V, unless otherwise specified. (Note 2)


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