Hardware Design Considerations

Freescale Semiconductor

7

Figure 3. Supply Voltage Sequencing and Separation Cautions

4.2.1

Power Up Sequence

high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond

to avoid turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 microsecond or slower rise time for all supplies.

4.2.2

Power Down Sequence

ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

Supplies Stable

2

1

3.3V

2.5V

1.5V

0

Time

NOTES:

IVDD should not exceed EVDD or SD VDD by more than 0.4V

at any time, including power-up.

Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to

0.9V, then separate for completion of ramps.

Input voltage must not be greater than the supply voltage (EVDD, SD VDD,

IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.

Use 1 microsecond or slower rise time for all supplies.

1.

2.

3.

4.