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MCF5474 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MCF5474 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 34 page Hardware Design Considerations MCF547x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 7 Figure 3. Supply Voltage Sequencing and Separation Cautions The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences. SD VDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 4.2.1 Power Up Sequence If EVDD/SD VDD are powered up with the IVDD at 0V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SD VDD to be in a high impedance state. There is no limit to how long after EVDD/SD VDD powers up before IVDD must power up. IVDD should not lead the EVDD, SD VDD, or PLL VDD by more than 0.4V during power ramp up or there is high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 microsecond or slower rise time for all supplies. 2. IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V, then separate for the completion of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 4.2.2 Power Down Sequence If IVDDPLL VDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLL VDD power down before EVDD or SD VDD must power down. IVDD should not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there is undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IVDD/PLL VDD to 0V 2. Drop EVDD/SD VDD supplies EVDD, SD VDD (3.3V) SD VDD (2.5V) IVDD, PLL VDD Supplies Stable 2 1 3.3V 2.5V 1.5V 0 Time NOTES: IVDD should not exceed EVDD or SD VDD by more than 0.4V at any time, including power-up. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to 0.9V, then separate for completion of ramps. Input voltage must not be greater than the supply voltage (EVDD, SD VDD, IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up. Use 1 microsecond or slower rise time for all supplies. 1. 2. 3. 4. |
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