Hardware Design Considerations

Freescale Semiconductor

9

4.4

USB Power Filtering

To minimize noise, an external filter is required for each of the USB power pins. The filter shown in Figure 6 should be

•

•

•

All traces should be as low impedance as possible, especially ground pins to the ground plane.

•

The filter for USB_PHYVDD to VSS should be connected to the power and ground planes, respectively, not fingers

of the planes.

•

In addition to keeping the filter components for the USB_PLLVDD as close as practical to the body of the processor

as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital

switching noise onto the portion of that supply between the filter and the processor.

•

The capacitors for C2 in the table below should be rated X5R or better due to temperature performance.

NOTE

In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel

with those shown.

Table 5. USB Filter Circuit Values

Nominal Voltage

R1 (

Ω)C1 (μF)

C2 (

μF)

USBVDD

(Bias generator supply)

3.3V

10

10

0.1

USB_PHYVDD

(Main transceiver supply)

3.3V

0

10

0.1

USB_PLLVDD

(PLL supply)

1.5V

10

1

0.1

USB_OSCVDD

(Oscillator supply)

3.3V

0

10

0.1

USB_OSCAVDD

(Oscillator analog supply)

1.5V

0

10

0.1

R1

C2

C1

GND