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MCF5484 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MCF5484 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 34 page  PLL Timing Specifications MCF548x ColdFire® Microprocessor, Rev. 4 Freescale Semiconductor 11 6 PLL Timing Specifications The specifications in Table 7 are for the CLKIN pin. Figure 8. Input Clock Timing Diagram Table 8 shows the supported PLL encodings. Figure 9 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers. Figure 9. CLKIN, Internal Bus, and Core Clock Ratios Table 7. Clock Timing Specifications Num Characteristic Min Max Units C1 Cycle time 20 40 ns C2 Rise time (20% of Vdd to 80% of vdd) — 2 ns C3 Fall time (80% of Vdd to 20% of Vdd) — 2 ns C4 Duty cycle (at 50% of Vdd) 40 60 % Table 8. MCF548x Divide Ratio Encodings AD[12:8]1 1 All other values of AD[12:8] are reserved. Clock Ratio CLKIN—PCI and FlexBus Frequency Range (MHz) Internal XLB, SDRAM Bus, and PSTCLK Frequency Range (MHz) Core Frequency Range (MHz) 00011 1:2 41.67–50.0 83.33–100 166.66–200 00101 1:2 25.0–41.67 50.0–83.332 2 DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz. Check with the memory component specifications to verify. 100.0–166.66 01111 1:4 25.0 100 200 CLKIN C4 C1 C4 C2 C3 25 40 50 60 70 70 80 90 100110120130140150160170180190200 60 25.0 50.0 100.0 CLKIN (MHz) Core Clock (MHz) Core Clock CLKIN 200.0 40 50 60 70 80 90 100 30 50.0 100.0 Internal Clock Internal Clock (MHz) 2x 2x 25.0 200.0 2x 4x 100.0 |
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