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TSC2101 Datasheet(PDF) 10 Page - Texas Instruments |
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TSC2101 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 95 page  TSC2101 SLAS392D− JUNE 2003 − REVISED MAY 2005 www.ti.com 10 SPI TIMING DIAGRAM ttd S S S S S S S E L ta MSB OUT BIT 6 .. .1 LSB OUT tsck tLead tLag twsck twsck tr tf tv tho tdis MSB IN BIT 6 .. .1 LSB IN thi tsu /SS SPISELZ SCLK SPISELZ SPICLK MISO SPISELZ MOSI SPISELZ TYPICAL TIMING REQUIREMENTS All specifications typical at 25°C, DVDD = 1.8 V(1) PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER MIN MAX MIN MAX UNITS twsck SCLK Pulse width 30 18 ns tLead Enable Lead Time 18 15 ns tLag Enable Lag Time 18 15 ns ttd Sequential Transfer Delay 18 15 ns ta Slave MISO access time 18 15 ns tdis Slave MISO disable time 18 15 ns tsu MOSI data setup time 6 6 ns thi MOSI data hold time 6 6 ns tho MISO data hold time 4 4 ns tv MISO data valid time 25 13 ns tr Rise Time 6 4 ns tf Fall Time 6 4 ns (1) These parameters are based on characterization and are not tested in production. |
Similar Part No. - TSC2101_08 |
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Similar Description - TSC2101_08 |
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