Electronic Components Datasheet Search |
|
TSC2101IRGZRG4 Datasheet(PDF) 11 Page - Texas Instruments |
|
TSC2101IRGZRG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 95 page TSC2101 SLAS392D− JUNE 2003 − REVISED MAY 2005 www.ti.com 11 AUDIO INTERFACE TIMING DIAGRAMS ts(DI) th(DI) td(DO−BCLK) td(DO−WS) WCLK BCLK SDOUT SDIN td(WS) Figure 1. I2S/LJ/RJ in Master Mode Typical Timing Requirements (see Figure 1) PARAMETER(1) IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER(1) MIN MAX MIN MAX UNITS td(WS) WCLK delay 30 15 ns td(DO−WS) WCLK to DOUT delay (for LJF mode) 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns tr Rise time 18 6 ns tf Fall time 18 6 ns (1) These parameters are based on characterization and are not tested in production. ts(DI) th(DI) td(DO−BCLK) WCLK BCLK SDOUT SDIN td(WS) td(WS) Figure 2. DSP Timing in Master Mode Typical Timing Requirements (see Figure 2) PARAMETER(1) IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER(1) MIN MAX MIN MAX UNITS td(WS) WCLK delay 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns tr Rise time 18 6 ns tf Fall time 18 6 ns (1) These parameters are based on characterization and are not tested in production. |
Similar Part No. - TSC2101IRGZRG4 |
|
Similar Description - TSC2101IRGZRG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |