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74VHC126T Datasheet(PDF) 1 Page - STMicroelectronics |
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74VHC126T Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 8 page 74VHC126 QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA June 1999 PIN CONNECTION AND IEC LOGIC SYMBOLS s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s HIGH NOISE IMMUNITY: VNIH =VNIL =28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 126 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.8V (Max.) DESCRIPTION The 74VHC126 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. This device requires the 3-STATE control input G to be set low to place the output into the high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ORDER CODES : 74VHC126M 74VHC126T M (Micro Package) T (TSSOP Package) ® 1/8 |
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