ICM7377B/7357B/7337B

Quad 12/10/8-Bit Voltage Output DACs

with Serial Interface and Adjustable Output Gain

Rev. A8

ICmic reserves the right to change the specifications without prior notice.

8

IC MICROSYSTEMS

DETAILED DESCRIPTION

The ICM7377B is a 12-bit voltage output quad DAC. The

ICM7357B is the 10-bit version of this family and the

ICM7337B is the 8-bit version.

This family of DACs employs a resistor string architecture

guaranteeing monotonic behavior. There is a 1.25V

onboard reference and an operating supply range of 2.7V

to 5.5V.

Reference Input

There are two reference inputs that can be driven from

the following equation:

Where D is the numeric value of DAC’s decimal input

bits, i.e. 12 for ICM7377B, 10 for ICM7357B and 8 for

ICM7337B.

Reference Output

The reference output is nominally 1.25V and is brought out

to a separate pin and can be used to drive external loads.

The outputs will nominally swing from 0 to 2.5V.

Output Amplifier

The Quad DAC has 4 output amplifiers with a wide output

swing. The actual swing of the output amplifiers will be

limited by offset error and gain error. See the Applications

Information Section for a more detailed discussion.

The 4 output amplifier’s inverting input of 4 DACs are

available to the user, allowing force and sense capability

for remote sensing and specific gain adjustment. The unity

gain can be provided by connecting the inverting input to

the output.

The output amplifier can drive a load of 2.0 k

GND in parallel with a 500 pF load capacitance.

The output amplifier has a full-scale typical settling time of

8 µs and it dissipates about 100 µA with a 3V supply

voltage.

Serial Interface and Input Logic

This quad DAC family uses a standard 3-wire connection

compatible with SPI/QSPI and Microwire interfaces. Data

is loaded in 16-bit words which consist of 4 address and

control bits (MSBs) followed by 12 bits of data (see table

1). The ICM7357 has the last 2 LSBs as don’t care and the

ICM7337 has the last 4 LSBs as don’t care. The DAC is

double buffered with an input latch and a DAC latch.

Serial Data Input

SDI (Serial Data Input) pin is the data input pin for All

DACs. Data is clocked in on the rising edge of SCK which

has a Schmitt trigger internally to allow for noise immunity

on the SCK pin. This specially eases the use for opto-

coupled interfaces.

The Chip Select pin which is the 8

package is active low. This pin must be low when data is

being clocked into the part. After the 16

Chip Select pin must be pulled high (level-triggered) for

the data to be transferred to an input bank of latches. This

pin also disables the SCK pin internally when pulled high

and the SCK pin must be low before this pin is pulled back

low. As the Chip Select pin is pulled high the shift register

contents are transferred to a bank of 16 latches (see

Figure 2.). The 4 bit control word (C3~C0) is then decoded

and the DAC is updated or loaded depending on the

control word (see Table 1).

The DAC has a double-buffered input with an input latch

and a DAC latch. The DAC output will swing to its new

value when data is loaded into the DAC latch. The user

has three options: loading only the input latch, updating

the DAC with data previously loaded into the input latch or

loading the input latch and updating the DAC at the same

time with a new code.

Serial Data Output

SDO (Serial Data Output) is the internal shift register’s

output. This pin can be used as the data output pin for

Daisy-Chaining and data readback. And it is compatible

with SPI/QSPI and Microwire interfaces.

Power-On Reset

There is a power-on reset on board that will clear the

contents of all the latches to all 0s on power-up and the

DAC voltage output will go to ground.

APPLICATIONS INFORMATION

Power Supply Bypassing and Layout

Considerations

As in any precision circuit, careful consideration has to be

given to layout of the supply and ground. The return path

from the GND to the supply ground should be short with

low impedance. Using a ground plane would be ideal. The

supply should have some bypassing on it. A 10 µF

tantalum capacitor in parallel with a 0.1 µF ceramic with a

low ESR can be used. Ideally these would be placed as

close as possible to the device. Avoid crossing digital and

analog signals, specially the reference, or running them

close to each other.

Output Swing Limitations

However, offset and gain error limit this ability. Figure 6

illustrates how a negative offset error will affect the output.

The output will limit close to ground since this is single

supply part, resulting in a dead-band area. As a larger

input is loaded into the DAC the output will eventually rise

above ground. This is why the linearity is specified for a

starting code greater than zero.

Figure 7 illustrates how a gain error or positive offset error

gain error or positive offset will cause the output to be

limited to the positive supply voltage resulting in a dead-

band of codes close to full-scale.