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X24C01SM Datasheet(PDF) 7 Page - IC MICROSYSTEMS |
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X24C01SM Datasheet(HTML) 7 Page - IC MICROSYSTEMS |
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7 / 14 page  X24C01 7 Sequential Read Sequential read is initiated in the same manner as the byte read. The first data byte is transmitted as with the byte read mode, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C01 continues to output data for each acknowledge received. The read operation is termi- nated by the master; by not responding with an acknowl- edge and by issuing a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 127) the counter “rolls over” to zero and the X24C01 continues to output data for each acknowledge re- ceived. Refer to Figure 8 for the address, acknowledge and data transfer sequence. Figure 8. Sequential Read 3837 FHD F13 Figure 9. Typical System Configuration MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER PULL-UP RESISTORS SDA SCL V CC 3837 FHD F14 BUS ACTIVITY: SDA LINE BUS ACTIVITY: X24C01 ADDRESS A C K A C K DATA n+x S T O P P DATA n A C K DATA n+1 A C K DATA n+2 R / W |
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