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X24012S Datasheet(PDF) 8 Page - IC MICROSYSTEMS |
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X24012S Datasheet(HTML) 8 Page - IC MICROSYSTEMS |
8 / 14 page X24012 8 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24012 SLAVE ADDRESS A C K A C K DATA n+x S T O P P DATA n A C K DATA n+1 A C K DATA n+2 Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24012 continues to out- put data for each acknowledge received. The read operation is terminated by the master, by not responding with an acknowledge and by issuing a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 127), the counter “rolls over” to address 0 and the X24012 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. Figure 9. Sequential Read Figure 10. Typical System Configuration 3847 FHD F14 3847 FHD F15 MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL V CC |
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