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X24C04PI Datasheet(PDF) 7 Page - IC MICROSYSTEMS |
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X24C04PI Datasheet(HTML) 7 Page - IC MICROSYSTEMS |
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7 / 18 page  X24C04 7 Current Address Read Internally the X24C04 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the X24C04 issues an acknowledge and transmits the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write opera- tion. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C04 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence. Figure 7. Current Address Read BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24C04 S T A R T SLAVE ADDRESS S S T O P P A C K DATA 3839 FHD F13 Figure 8. Random Read 3839 FHD F14 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24C04 S T A R T SLAVE ADDRESS S S T O P P A C K A C K A C K WORD ADDRESS n SLAVE ADDRESS DATA n S T A R T S |
Similar Part No. - X24C04PI |
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Similar Description - X24C04PI |
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