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X25128SMG Datasheet(PDF) 5 Page - IC MICROSYSTEMS |
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X25128SMG Datasheet(HTML) 5 Page - IC MICROSYSTEMS |
5 / 15 page X25128 5 be low when HOLD is first pulled low and SCK must also be low when HOLD is released. The HOLD input may be tied high either directly to VCC or tied to VCC through a resistor. Operational Notes The X25128 powers-up in the following state: • The device is in the low power standby state. • A high to low transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: • The “write enable” latch is reset upon power-up. • A WREN instruction must be issued to set the “write enable” latch. • CS must come high at the proper clock count in order to start a write cycle. Figure 1. Read E2PROM Array Operation Sequence Figure 2. Read Status Register Operation Sequence 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 16 BIT ADDRESS 15 14 13 3 2 1 0 3091 FM F03 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 7 6 5 4 3 2 1 0 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION 3091 FM F04 |
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