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EUA5312 Datasheet(PDF) 3 Page - Eutech Microelectronics Inc |
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EUA5312 Datasheet(HTML) 3 Page - Eutech Microelectronics Inc |
3 / 18 page EUA5312 DS5312 Ver 1.7 May. 2005 3 Pin Configurations Package Pin Configurations(Top View) TSSOP-24 with a Thermal Pad exposure on the bottom of the package Pin Description PIN PIN I/O DESCRIPTION BYPASS 11 Tap to voltage divider for internal mid-supply bias generator GAIN0 2 I Bit 0 of gain control GAIN1 3 I Bit 1 of gain control GND 1,12 13,24 Ground connection for circuitry. Connected to thermal pad. LHPIN 6 I Left channel headphone input, selected when BTL SE/ is held high. LIN 10 I Common left input for fully differential input. AC ground for single-ended inputs. LLINEIN 5 I Left channel line input, selected when BTL SE/ is held low. LOUT+ 4 O Left channel positive output in BTL mode and positive output in SE mode. LOUT- 9 O Left channel negative output in BTL mode and high-impedance in SE mode. PC-BEEP 14 I The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak) square wave is input to PC-BEEP or PCB ENABLE is high. LINE HP/ 17 I LINE HP/ is the input MUX control input. When the LINE HP/ terminal is held high, the headphone inputs (LHPIN or RHPIN [6, 20]) are active. When the LINE HP/ terminal is held low, the line BTL inputs (LLINEIN or RLINEIN [5, 23]) are active. PVDD 7,18 I Power supply for output stage. RHPIN 20 I Right channel headphone input, selected when BTL SE/ is held high RIN 8 I Common right input for fully differential input. AC ground for single-ended inputs. RLINEIN 23 I Right channel line input, selected when BTL SE/ is held low. ROUT+ 21 O Right channel positive output in BTL mode and positive output in SE mode. ROUT- 16 O Right channel negative output in BTL mode and high-impedance in SE mode. SHUTDOWN 22 I When held low, this terminal place the entire device, except PC-BEEP detect circuitry, in shutdown mode. BTL SE/ 15 I Input and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected. VDD 19 I Analog VDD input supply. This terminal needs to be isolated from PVDD to achieve highest performance. |
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