EUP7559

DS7559 Ver 1.0 May. 2007

3

Pin Configurations

Package Type

Pin

Configurations

TDFN-8

Pin Description

PIN

Pin

DESCRIPTION

INA

1

LDO A Regulator Input. Connect to INB. Input voltage can range from 2.5V to 6V. Bypass

INA with a ceramic capacitor to GND.

ENA

2

Shutdown A Input. A logic-low on ENA shuts down regulator A. If ENA and ENB are both

low, both regulators and the internal reference are off and the supply current is reduced to

10nA (typ). If either ENA or ENB is a logic high, the internal reference is on. Connect

ENA to INA for always-on operation of regulator A.

ENB

3

low, both regulators and the internal reference are off and the supply current is reduced to

10nA (typ). If either ENA or ENB is a logic high, the internal reference is on. Connect

ENB to INB for always-on operation of regulator B.

INB

4

LDO B Regulator Input. Connect to INA. Input voltage can range from 2.5V to 6V. Bypass

INB with a ceramic capacitor to GND.

OUTB

5

Regulator B Output. OUTB can source up to 300mA continuous current. Bypass OUTB

with a ceramic capacitor to GND. During shutdown, OUTB is internally discharged to

GND through a 300Ω. resistor.

GND

6

Ground.

BP

7

Reference Noise Bypass. Bypass BP with a low-leakage 0.01µF ceramic capacitor for

reduced noise at both outputs.

OUTA

8

Regulator A Output. OUTA can source up to 300mA continuous current. Bypass OUTA

with a ceramic capacitor to GND. During shutdown, OUTA is internally discharged to

GND through a 300Ω. resistor.