Dual/Triple-Voltage

µP Supervisory Circuits

8

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During the normal operating mode, the supervisor will

issue a reset pulse for the reset timeout period (140ms

min) if the µP does not update the WDI with a valid tran-

sition (HIGH to LOW or LOW to HIGH) within the stan-

dard timeout period (1.6s min).

watchdog reset), there is an initial watchdog startup

timeout period of 25.6s. The startup mode provides an

extended period for the system to power up and fully

initialize all µP and system components before assum-

ing responsibility for routine watchdog updates. The

normal watchdog timeout period (1.6s min) begins at

the conclusion of the startup timeout period or after the

first transition on WDI before the conclusion of the start-

up period (Figure 3).

Applications Information

Ensuring a Valid

RESET Output

In some systems, it is necessary to ensure a valid reset

cuit shown in Figure 4. Note that this configuration does

not work for the open-drain outputs of the MAX6352/

MAX6355/MAX6358.

Interfacing to µPs with

Bidirectional Reset Pins

Microprocessors with bidirectional reset pins will con-

tend with the push-pull outputs of these devices. To

prevent this, connect a 4.7k

Ω resistor between RESET

and the µP’s reset I/O port, as shown in Figure 5. Buffer

RESET as shown in the figure if this reset is used by

other components in the system.

GND

100k

Ω

RST2

RST1

RST

MAX6351 MAX6356

MAX6353 MAX6357

MAX6354 MAX6359

MAX6360

Figure 5. Interfacing to µPs with Bidirectional Reset I/O

BUFFERED RESET TO OTHER SYSTEM COMPONENTS

4.7k

Ω

GND

RESET

µP

GND

RST2

RST1

RST

MAX6351–MAX6360

1.6s

MAX

1.6s MAX

25.6s MAX

WDI

RESET

140ms

Figure 3. Normal Watchdog Startup Sequence

Chip Information

TRANSISTOR COUNT: 855