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ADC12L032 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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ADC12L032 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 35 page DC and Logic Electrical Characteristics The following specifications apply for V + =V A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver- sion mode, f CK =fSK = 5 MHz, RS =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for TA =TJ = T MIN to TMAX; all other limits TA =TJ = 25˚C. (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS V IN(1) Logical “1” Input Voltage V + = 3.6V 2.0 V (min) V IN(0) Logical “0” Input Voltage V + = 3.0V 0.8 V (max) I IN(1) Logical “1” Input Current V IN = 3.3V 0.005 1.0 µA (max) I IN(0) Logical “0” Input Current V IN = 0V −0.005 −1.0 µA (min) DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS V OUT(1) Logical “1” Output Voltage V + = 3.0V, I OUT = −360 µA 2.4 V (min) V + = 3.0V, I OUT =−10µA 2.9 V (min) V OUT(0) Logical “0” Output Voltage V + = 3.0V, I OUT = 1.6 mA 0.4 V (max) I OUT TRI-STATE Output Current V OUT = 0V −0.1 −3.0 µA (max) V OUT = 3.3V 0.1 3.0 µA (max) +I SC Output Short Circuit Source Current V OUT =0V 14 6.5 mA (min) −I SC Output Short Circuit Sink Current V OUT =VD+16 8.0 mA (min) POWER SUPPLY CHARACTERISTICS I D+ Digital Supply Current Awake 1.1 1.5 mA (max) CS = HIGH, Powered Down, CCLK on 600 µA CS = HIGH, Powered Down, CCLK off 12 µA I A+ Positive Analog Supply Current Awake 2.2 3.0 mA (max) CS = HIGH, Powered Down, CCLK on 10 µA CS = HIGH, Powered Down, CCLK off 0.1 µA I REF Reference Input Current Awake 70 µA CS = HIGH, Powered Down 0.1 µA AC Electrical Characteristics The following specifications apply for V + =V A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver- sion mode, t r =tf = 3 ns, fCK =fSK = 5 MHz, RS =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) f CK Conversion Clock (CCLK) Frequency 10 5 MHz (max) 1 MHz (min) f SK Serial Data Clock SCLK Frequency 10 5 MHz (max) 0 Hz (min) Conversion Clock Duty Cycle 40 % (min) 60 % (max) Serial Data Clock Duty Cycle 40 % (min) 60 % (max) t C Conversion Time 12-Bit + Sign or 12-Bit 44(t CK) 44(t CK) (max) 8.8 µs (max) 8-Bit + Sign or 8-Bit 21(t CK) 21(t CK) (max) 4.2 µs (max) www.national.com 6 |
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