ADC12L038 datasheet(3/35 Pages) NSC

Part #	ADC12L038

Description	3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

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Manufacturer	NSC [National Semiconductor (TI)]

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Pin Descriptions

CCLK

The clock applied to this input controls the suc-

cessive approximation conversion and the ac-

quisition time. The rise and fall times of the

clock edges should not be longer than 1 µs.

SCLK

This serial data clock input clocks out the serial

data. The rising edge at this pin loads the infor-

mation at the DI pin into the multiplexer address

and mode select shift register. This address

controls which channel of the analog input mul-

tiplexer (MUX) is selected and the mode of

operation for the A/D. With CS low the falling

edge of SCLK shifts the data resulting from the

previous ADC conversion out at DO, with the

exception of the first bit of data. When CS is low

continuously, the first bit of the data is clocked

out on the rising edge of EOC (end of conver-

sion). When CS is toggled, the falling edge of

CS always clocks out the first bit of data. CS

should be brought low while SCLK is low. The

rise and fall times of the clock edges should not

be longer than 1 µs.

DI

The data applied to this serial data input pin is

shifted into the multiplexer address and mode

select register on the rising edge of SCLK.

Tables 2, 3, 4, 5 show the assignment of the

multiplexer address and the mode select data.

DO

This pin is the active push/pull output pin when

CS is Low. When CS is High this output is off

(high impedance). The A/D conversion result

(DB0–DB12) and converter status data are

clocked out on this pin at the falling edge of

SCLK. The word length and format of this result

can vary (see Table 1). The word length and

format are controlled by the data shifted into the

multiplexer address and mode select register

(see Table 5).

EOC

This active push/pull output indicates the status

of the ADC. When low the A/D is busy with a

conversion,

auto-calibration,

auto-zero

or

power down cycle. The rising edge of EOC

signals the end of one of these cycles.

CS

When a logic low is applied to this chip select

pin, the rising edge of SCLK shifts the data at

DI into the address register and brings DO out

of the high impedance state. With CS low, the

falling edge of SCLK shifts the data resulting

from the previous ADC conversion out at DO,

with the exception of the first bit of data. When

CS is low continuously, the first bit of the data is

clocked out on the rising edge of EOC (end of

conversion). When CS is toggled the falling

edge of CS always clocks out the first bit of

data. CS should be brought low while SCLK is

low. The falling edge of CS halts a conversion

in progress (the data in the output latches may

be corrupted) and starts the sequence for a

new conversion. Therefore, when CS is brought

low during a conversion in progress the data

output at that time should be ignored. CS may

also be left continuously low, in which case it is

imperative that the correct number of SCLK

cycles be applied to the ADC in order to remain

synchronous. After the ADC supply power is

applied, the ADC expects to see 13 clock

cycles for each I/O sequence. After that, the

number of clock cycles the ADC expects is the

same as the digital output word length, which

can be modified by the user. See Table 5.

DOR

This data output ready pin is an active push/pull

output. It is low when the conversion result is

being shifted out and goes high to signal that all

the data has been shifted out.

CONV

A logic low is required on this pin to program

any mode or change the ADC’s configuration.

(See the Table 5, Mode Programming). When

this pin is high, the ADC is placed into the read

data only mode. While in this mode, bringing

CS low and pulsing SCLK will only clock out

any data stored in the ADCs output shift regis-

ter. The data at DI will be neglected, a new

conversion will not be started and the ADC will

remain in the mode and/or configuration previ-

ously programmed. Read data only cannot be

performed while a conversion, Auto-Cal or

Auto-Zero is in progress.

PD

When this power down pin is high, the A/D is

powered down; when PD is low the A/D is

powered up. The A/D takes a maximum of 700

µs to power up after the command is given.

CH0–CH7

These are the analog inputs of the MUX. A

channel input is selected by the address infor-

mation at the DI pin (see Tables 2, 3, 4).

The voltage applied to these inputs should not

exceed V

A+ or go below GND. Exceeding this

range on an unselected channel will corrupt the

reading of a selected channel.

COM

This analog input pin is used as a pseudo

ground

when

the

analog

multiplexer

is

single-ended.

MUXOUT1, MUXOUT2

These

are

the

multiplexer

output

pins.

A/DIN1,

A/DIN2

These are the converter input pins. MUXOUT1

is usually tied to A/DIN1. MUXOUT2 is usually

tied to A/DIN2. If external circuitry is placed

between MUXOUT1 and A/DIN1, or MUXOUT2

and A/DIN2 it may be necessary to protect

these pins. The voltage at these pins should not

exceed V

A

+ or go below AGND (see Figure 6 ).

V

REF+

This is the positive analog voltage reference

input. In order to maintain accuracy the voltage

range of V

REF =(VREF+)−(VREF−) is 1 VDC to

3.3 V

DC and VREF+ cannot exceed VA+.

V

REF−

The negative voltage reference input. To main-

tain accuracy, this voltage must not go below

GND or exceed (V

REF+) − 1V. (See Figure 5).

V

A+, VD+

These analog and digital power supply pins are

not connected together on the chip and should

be tied to the same power supply but bypassed

separately (see Figure 5 ). The operating volt-

age range of V

A+ and VD+ is 3.0 VDC to 5.5

V

DC.

DGND

Digital ground pin (see Figure 5 ).

AGND

Analog ground pin (see Figure 5 ).

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ADC12L038 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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