UCC28220, UCC28221

SLUS544C − SEPTEMBER 2003 − REVISED OCTOBER 2007

3

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ABSOLUTE MAXIMUM RATINGS

Parameter

UCC2822X

UNIT

High voltage start-up input, VIN

110

V

Supply voltage, VDD

15

V

Output current (OUT1, OUT2) dc , IOUT(dc)

±10

mA

OUT1/ OUT2 capacitive load

200

pF

REF output current, IREF

10

mA

Current sense inputs, CS1, CS2

−1.0 to 2.0

V

Analog inputs (CHG, DISCHG, SLOPE, REF, CNTRL)

−0.3 to 3.6

V

Analog inputs (SS, LINEOV, LINEUV, LINEHYS)

−0.3 to 7.0

V

Power dissipation at TA = 25°C (PW package)

400

mW

Power dissipation at TA = 25°C (D package)

650

mW

Junction operating temperature, TJ

−55 to 150

°C

Storage temperature, Tstg

−65 to 150

°C

Lead temperature (soldering, 10 sec.), Tsol

300

°C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability.

‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook

for thermal limitations and considerations of packages.

ELECTRICAL CHARACTERISTICS:

105

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNITS

Overall Section

Operating VDD range

8

14

V

Quiescent current

SS = 0 V, no switching, Fosc = 1 MHz

1.5

3

4

mA

Operating current

Outputs switching, Fosc = 1 MHz

1.6

3.5

6

mA

Startup Section

Startup current

UCC28220 VDD < (UVLO−0.8)

200

µA

UVLO start threshold

UCC28220

9.5

10

10.5

UVLO start threshold

UCC28221

12.3

13

13.7

V

UVLO stop threshold

7.6

8

8.4

V

UVLO hysteresis

UCC28220

1.8

2

2.2

V

UVLO hysteresis

UCC28221

4.8

5

5.2

JFET ON threshold

SS = 0, outputs not switching, VDD decreasing

9.5

10

10.5

V

JFET ON threshold

SS = 2 V,Cntrl = 2 V, output switching, VDD decreasing;

same threshold as UVLO stop

7.6

8

8.4

V

High voltage JFET current

VIN = 36 V to 76 V, VDD = 0 V

16

48

100

High voltage JFET current

VIN = 36 V to 76 V, VDD = 10 V

4

16

40

mA

High voltage JFET current

VIN = 36 V to 76 V, VDD < UVLO

4

12

40

mA

JFET leakage

VIN = 36 V to 76 V, VDD = 14 V

100

µA