UCC28220, UCC28221

SLUS544C − SEPTEMBER 2003 − REVISED OCTOBER 2007

10

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APPLICATION INFORMATION

15

1

2

R2

R1

R3

Input

Voltage

+

UV

HYS

OV

+

1.26 V

+

1.26 V

LINE_GOOD

S1

OPEN

S2

CLOSED

1.26 V

R4

Figure 1. Line UVLO and OVLO Functional Diagram

V1

V2

V3

V4

LINE_GOOD

ENABLE

OFF

Figure 2. Line UVLO and OVLO Operation

VDD

Because the driver output impedance is high the energy storage requirements on the VDD capacitor is low. For

improved noise immunity it is recommended that the VDD pin, be bypassed with a minimum of 0.1

µF of

capacitance to GND. In most typical applications the bias voltage for the MOSFET drivers will also be used as

the VDD supply voltage for the chip. In the aforementioned applications it is beneficial to add a low valued

resistor between the bulk storage capacitor of the driver and the VDD capacitor for the UCC28220/1. By adding

a resistor in series with the bias supply any noise that is present on the bias supply will be filtered out before

getting to the VDD pin of the controller.