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HA0018E Datasheet(PDF) 7 Page - Holtek Semiconductor Inc |
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HA0018E Datasheet(HTML) 7 Page - Holtek Semiconductor Inc |
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7 / 34 page  HT48RA0-3/HT48CA0-3 Rev.1.10 7 October 12, 2007 With the exception of the TO and PDF flags, the other status register bits can be altered by instructions like most other register. Any data written into the status regis- ter will not change the TO or PDF flags. In addition it should be noted that operations related to the status reg- ister may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, device power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the sub- routine can corrupt the status register, precautions must be taken to save it properly. Oscillator Configuration Only an external RC oscillator type is supported for the HT48RA0-3/HT48CA0-3. An external resistor between OSC1 and VSS in needed whose resistance must be 12k W for a 4MHz frequency. The RC oscillator provides ± 3% accuracy, the condi- tions are: · V DD= 2.0V ~ 3.6V · Temperature = 0 °C ~ +50°C · f SYS= 4MHz Watchdog Timer - WDT The WDT clock source is implemented by the instruction clock which is the system clock divided by 4. The clock source is processed by a frequency divider and a prescaler to provide various time out periods. WDT time out period = Clock Source 2 n Where n= 8~11 selected by a configuration option. The WDT timer is designed to prevent a software mal- function or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation and the WDT will lose its protection pur- pose. In this situation the logic can only be restarted by external logic. A WDT overflow under normal operation will initialise a ²chip reset² and set the status bit ²TO². To clear the con- tents of the WDT prescaler, two methods are adopted, software instructions or a HALT instruction. There are two types of software instructions. One type is the single in- struction ²CLR WDT², the other type comprises two in- structions, ²CLR WDT1² and ²CLR WDT2². Of these two types of instructions, only one can be active depending on the configuration option -²CLR WDT times selection op- tion ².Ifthe ²CLR WDT² is selected (i.e.. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e.. CLR WDT times equal two), these two in- structions must be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. R C O s c i l l a t o r O S C 1 1 2 k W System Oscillator 2 n C l o c k S o u r c e ( S y s t e m C l o c k / 4 ) 3 - b i t C o u n t e r P r e s c a l l e r ( 8 - b i t ) W D T T i m e - o u t C o d e O p t i o n S e l e c t C o d e O p t i o n C l e a r W D T F r e q u e n c y D i v i d e r C l o c k S o u r c e ( n = 8 ~ 1 1 ) Watchdog Timer |
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