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SN55LVDS32 Datasheet(PDF) 6 Page - Texas Instruments |
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SN55LVDS32 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 22 page SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS262H – JULY 1997 – REVISED MARCH 2000 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SN65LVDS32, SN65LVDS3486, SN65LVDS9637 UNIT MIN TYP† MAX VITH+ Positive-going differential input voltage threshold See Figure 2 and Table 1 100 mV VITH– Negative-going differential input voltage threshold‡ See Figure 2 and Table 1 –100 mV VOH High-level output voltage IOH = –8 mA 2.4 V VOL Low-level output voltage IOL = 8 mA 0.4 V SN65LVDS32, Enabled, No load 10 18 ICC Supply current , SN65LVDS3486 Disabled 0.25 0.5 mA SN65LVDS9637 No load 5.5 10 II Input current (A or B inputs) VI = 0 –2 –10 –20 µA II Input current (A or B inputs) VI = 2.4 V – 1.2 –3 µA II(OFF) Power-off input current (A or B inputs) VCC = 0, VI = 3.6 V 6 20 µA IIH High-level input current (EN, G, or G inputs) VIH = 2 V 10 µA IIL Low-level input current (EN, G, or G inputs) VIL = 0.8 V 10 µA IOZ High-impedance output current VO = 0 or VCC ±10 µA † All typical values are at TA = 25°C and with VCC = 3.3 V. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going differential input voltage threshold only. SN65LVDSxxxx switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SN65LVDS32, SN65LVDS3486, SN65LVDS9637 UNIT MIN TYP MAX tpLH Propagation delay time, low-to-high-level output 1.5 2.1 3 ns tpHL Propagation delay time, high-to-low-level output 1.5 2.1 3 ns tsk(p) Pulse skew (|tPHL – tPLH|) 0 0.4 ns tsk(o) Channel-to-channel output skew† CL = 10 pF, See Figure 3 0.1 0.3 ns tsk(pp) Part-to-part skew‡ 1 ns tr Output signal rise time, 20% to 80% 0.6 ns tf Output signal fall time, 80% to 20% 0.7 ns tpHZ Propagation delay time, high-level-to-high-impedance output 6.5 12 ns tpLZ Propagation delay time, low-level-to-high-impedance output See Figure 4 5.5 12 ns tpZH Propagation delay time, high-impedance-to-high-level output See Figure 4 8 12 ns tpZL Propagation delay time, high-impedance-to-low-level output 3 12 ns † tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ‡ tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. |
Similar Part No. - SN55LVDS32_00 |
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Similar Description - SN55LVDS32_00 |
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