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TMX3C6414EGLZA5E0 Datasheet(PDF) 8 Page - Texas Instruments |
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TMX3C6414EGLZA5E0 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 139 page TMS320C6414, TMS320C6415, TMS320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS146L − FEBRUARY 2001 − REVISED JULY 2004 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 device characteristics Table 1 provides an overview of the C6414, C6415, and C6416 DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6414, C6415, and C6416 Processors HARDWARE FEATURES C6414, C6415, AND C6416 EMIFA (64-bit bus width) (default clock source = AECLKIN) 1 Peripherals EMIFB (16-bit bus width) (default clock source = BECLKIN) 1 Not all peripherals pins are available at the EDMA (64 independent channels) 1 are available at the same time. (For more HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) same time. (For more details, see the Device Configuration section.) PCI (32-bit) [DeviceID Register value 0xA106] 1 [C6415/C6416 only] details, see the Device Configuration section.) Peripheral performance McBSPs (default internal clock source = CPU/4 clock frequency) 3 Peripheral performance is dependent on UTOPIA (8-bit mode) 1 [C6415/C6416 only] is dependent on chip-level configuration. 32-Bit Timers (default internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output 0 (GP0) 16 Decoder Coprocessors VCP 1 (C6416 only) Decoder Coprocessors TCP 1 (C6416 only) Size (Bytes) 1056K On-Chip Memory Organization 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 1024KB Unified Mapped RAM/Cache (L2) CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01 Device_ID Silicon Revision Identification Register (DEVICE_REV [19:16]) Address: 0x01B0 0200 DEVICE_REV[19:16] Silicon Revision 1111 1.03 or earlier 0001 1.03 0010 or 0000 1.1 0011 2.0 Frequency MHz 500, 600, 720 Cycle Time ns 2 ns (C6414-5E0, C6415-5E0, C6416-5E0) and (C6414A-5E0, C6415A-5E0, C6416A-5E0) [500-MHz CPU, 100-MHz EMIF]† 1.67 ns (C6414-6E3, C6415-6E3, C6416-6E3) and (C6414A-6E3, C6415A-6E3, C6416A-6E3) [600-MHz CPU, 133-MHz EMIFA]† 1.39 ns (C6414-7E3, C6415-7E3, C6416-7E3) [720-MHz CPU, 133-MHz EMIFA]† Voltage Core (V) 1.2 V (-5E0) 1.25 V (A-5E0) 1.4 V (-6E3, A-6E3, -7E3) I/O (V) 3.3 V PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12 BGA Package 23 x 23 mm 532-Pin BGA (GLZ and ZLZ) Process Technology µm 0.13 µm Product Status Product Preview (PP), Advance Information (AI), Production Data (PD) PD, AI‡ † On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data sheet. ‡ The extended temperature devices for silicon revision 2.0 (C641x A-5E0, C641xA-6E3) are at the advance information (AI) stage of development. All other devices are at the Production Data (PD) stage of development. |
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