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MAX19713 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX19713 Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 37 page  10-Bit, 45Msps, Full-Duplex Analog Front-End 6 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Integral Nonlinearity INL ±0.6 LSB Supply Current 210 µA AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution N 12 Bits Integral Nonlinearity INL From code 100 to code 4000 ±1.25 LSB Differential Nonlinearity DNL Guaranteed monotonic over code 100 to code 4000 (Note 6) -1.0 ±0.65 +1.2 LSB Output-Voltage Low VOL RL > 200k Ω 0.2 V Output-Voltage High VOH RL > 200k Ω 2.57 V DC Output Impedance DC output at midscale 4 Ω Settling Time From code 1024 to code 3072, within ±10 LSB 1µs Glitch Impulse From code 0 to code 4095 24 nV•s Rx ADC–Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid tDOI Figure 3 (Note 6) 5.5 8.2 12.5 ns CLK Fall to Channel-Q Output Data Valid tDOQ Figure 3 (Note 6) 6.5 9.5 13.6 ns I-DAC DATA to CLK Fall Setup TimetDSI Figure 5 (Note 6) 10 ns Q-DAC DATA to CLK Rise Setup Time tDSQ Figure 5 (Note 6) 10 ns CLK Fall to I-DAC Data Hold Time tDHI Figure 5 (Note 6) 0 ns CLK Rise to Q-DAC Data Hold Time tDHQ Figure 5 (Note 6) 0 ns CLK Duty Cycle 50 % CLK Duty-Cycle Variation ±10 % Digital Output Rise/Fall Time 20% to 80% 2.4 ns SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 6) Falling Edge of CS/WAKE to Rising Edge of First SCLK Time tCSS 10 ns DIN to SCLK Setup Time tDS 10 ns DIN to SCLK Hold Time tDH 0ns SCLK Pulse-Width High tCH 25 ns SCLK Pulse-Width Low tCL 25 ns SCLK Period tCP 50 ns SCLK to CS/WAKE Setup Time tCS 10 ns CS/WAKE High Pulse Width tCSW 80 ns CS/WAKE High to DOUT Active High tCSD Bit AD0 set 200 ns |
Similar Part No. - MAX19713 |
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Similar Description - MAX19713 |
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