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SST29LE010A-90-4I-P Datasheet(PDF) 1 Page - Silicon Storage Technology, Inc |
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SST29LE010A-90-4I-P Datasheet(HTML) 1 Page - Silicon Storage Technology, Inc |
1 / 26 page 1 1 Megabit (128K x 8) Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A Data Sheet © 1999 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 303-01 2/99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FEATURES: • Single Voltage Read and Write Operations – 5.0V-only for the SST29EE010A – 3.0-3.6V for the SST29LE010A – 2.7-3.6V for the SST29VE010A • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V – Standby Current: 10 µA (typical) • Fast Page Write Operation – 128 Bytes per Page, 1024 Pages – Page Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 5 sec (typical) – Effective Byte Write Cycle Time: 39 µs (typical) • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 3.0-3.6V operation: 150 and 200 ns – 2.7-3.6V operation: 200 and 250 ns • Latched Address and Data • Automatic Write Timing – Internal VPP Generation • End of Write Detection – Toggle Bit – Data# Polling • Hardware and Software Data Protection • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32 Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 20mm & 8mm x 14mm) PRODUCT DESCRIPTION The SST29EE010A/29LE010A/29VE010A are 128K x 8 CMOS Page Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash tech- nology. The split-gate cell design and thick oxide tunnel- ing injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010A/29LE010A/29VE010A write with a single power supply. Internal Erase/Program is transpar- ent to the user. The SST29EE010A/29LE010A/ 29VE010A conform to JEDEC standard pinouts for byte- wide memories. Featuring high performance page write, the SST29EE010A/29LE010A/29VE010A provide a typical byte-write time of 39 µsec. The entire memory, i.e., 128 KBytes, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the SST29EE010A/29LE010A/29VE010A have on-chip hardware and software data protection schemes. De- signed, manufactured, and tested for a wide spectrum of applications, the SST29EE010A/29LE010A/29VE010A are offered with a guaranteed page write endurance of 104 cycles. Data retention is rated at greater than 100 years. The SST29EE010A/29LE010A/29VE010A are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE010A/29LE010A/ 29VE010A significantly improve performance and reli- ability, while lowering power consumption. The SST29EE010A/29LE010A/29VE010A improve flexibil- ity while lowering the cost for program, data, and configu- ration storage applications. To meet high density, surface mount requirements, the SST29EE010A/29LE010A/29VE010A are offered in 32- pin TSOP and 32-lead PLCC packages. A 600-mil, 32- pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST page mode EEPROM offers in-circuit electrical write capability. The SST29EE010A/29LE010A/ 29VE010A does not require separate Erase and Program operations. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE010A/29LE010A/29VE010A have industry standard Software Data Protection. The SST29EE010A/29LE010A/29VE010A are compatible with industry standard EEPROM pinouts and functionality. Read The Read operations of the SST29EE010A/29LE010A/ 29VE010A are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. |
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