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MS6712GU Datasheet(PDF) 8 Page - MOSA ELECTRONICS |
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MS6712GU Datasheet(HTML) 8 Page - MOSA ELECTRONICS |
8 / 17 page MOSA MS6712 4 Stereo Inputs / 4-Channel Outputs Audio Processor REV1.0 8 www.mosanalog.com Timing of SDA and SCL Bus Lines tf S tLOW tHD;STA tr tHD;DAT tSU;DAT tf tHIGH tHD;STA tSU;STA Sr S P tSP tSU;STO tr tBUF SDA SCL Standard Mode Symbol Parameter Min Max Unit fSCL SCL clock frequency 0 100 kHz tHD:STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 - us tLOW LOW period of the SCL clock 4.7 - us tHIGH HIGH period of the SCL clock 4.0 - us tSU:STA Set-up time for a repeated START condition 4.7 - us tHD:DAT Data hold time: For I 2C-bus devices 0 3.45 us tSU:DAT Data-set-up time 250 - ns tr Rise time of both SDA and SCL signals - 1000 ns tf Fall time of both SDA and SCL signals - 300 ns tSU:STO Set-up time for STOP condition 4.0 - us tBUF Bus free time between a STOP and START condition 4.7 - us Cb Capacitive load for each bus line - 400 pF VnL Noise margin at the LOW level for each connected device (including hysteresis) 0.1VDD - V VnH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2VDD - V BUS INTERFACE Data are transmitted to and from the MCU to the MS6712 via the SDA and SCL. The SDA and SCL make up the BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage. SDA (Serial Data Line) Rp Rp SCL (Serial Clock Line) Pull up resistors V DD MCU MS6712 |
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