 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TPS40180RGET Datasheet(PDF) 7 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
TPS40180RGET Datasheet(HTML) 7 Page - Texas Instruments |
|
|
7 / 52 page  www.ti.com TERMINAL INFORMATION TPS40180 SLVS753B – FEBRUARY 2007 – REVISED NOVEMBER 2007 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. FB 1 I Inverting input to the internal error amplifier. Normally this pin is at the reference voltage of 700 mV. Output of the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for output DIFFO 2 O voltage sensing at the load to eliminate distribution drops. Positive input to the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for VOUT 3 I output voltage sensing at the load to eliminate distribution drops. Negative input to the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for GSNS 4 I output voltage sensing at the load to eliminate distribution drops. Pin is either an input or an output. If the chip is configured as a voltage loop master the valley voltage is output on this pin and is distributed to the slave devices. If configured as a voltage loop slave, the master VSH 5 I/O VSH pin is connected here and the device uses the master valley voltage reference to improve current sharing. Programs the overcurrent limit of the device. Connecting a resistor from this pin to VSH and another to VOUT on the voltage loop master sets a voltage above VSH. COMP is not allowed to exceed this voltage. If ILIM 6 I the load current requirements force COMP to this level for seven clock cycles, an overcurrent event is declared, and the system shuts down and enter a hiccup fault recovery mode. The controller attempts to restart after a time period given by seven soft-start cycles. Soft-start input. This pin determines the startup ramp time for the converter as well as overcurrent and other fault recovery timing. The voltage at this pin is applied as a reference to the error amplifier. While this voltage is below the precision 700 mV reference, it acts as the dominant reference to the error amp providing a closed loop startup. After it rises above the 700 mV precision reference, the 700 mV precision SS 7 I reference dominates and the output regulates at the programmed level. In case of an overcurrent event, the converter attempts to restart after a period of time defined by seven soft-start cycles. Additionally this pin is used to configure the chip as a voltage loop master or slave. If the pin is tied to VDD or PVCC at power up, the device is in voltage loop slave mode. Otherwise, the device is a voltage loop master. Frequency programming pin. Connecting a resistor from this pin to GND sets the switching frequency of the RT 8 I device. If this pin is connected to VDD or PVCC, the device is a clock slave and gets its time base from CLKIO of the clock master device. Phase addressing is done on PSEL. Signal level ground connection for the device. All low level signals at the device should be referenced to this GND 9 – pin. No power level current should be allowed to flow through the GND pin copper areas on the board. Connect to the thermal pad area, and from there to the PGND copper area. Electrically quiet 5-V supply for the internal circuitry inside the device. If VDD is above 5 V, connect a 20- Ω BP5 10 I resistor from PVCC to this pin and a 100-nF capacitor from this pin to GND. For VDD at 5 V, this pin can be tied directly to VDD or through a 20- Ω resistor with a 100-nF decoupling capacitor to reduce internal noise. UVLO input for the device. A resistor divider from VDD sets the turn on voltage for the device. Below this UVLO 11 I voltage, the device is in a low quiescent current state. Pulling this pin to ground shuts down the device, and is used as a system shutdown method. VDD 12 I Power input for the LDO on the device. Common connection for the power circuits on the device. This pin should be electrically close to the source PGND 13 – of the FET connected to LDRV. Connected to GND only at the thermal pad for best results. LDRV 14 O Gate drive output for the low-side or rectifier FET. Output of the on board LDO. This is the power input for the drivers and bootstrap circuit. The 5.3-V output PVCC 15 O on this pin is used for external circuitry as long as the total current required to drive the gates of the switching FETs and external loads is less than 50 mA. Connect a 1 µF capacitor from this pin to GND. This pin is connected to the source of the high-side or switch FET and is the return path for the floating SW 16 O high-side driver. Gate drive output for the high-side FET. High-side FET turn-on time must not be greater than minimum HDRV 17 O on-time. See electrical characteristics table for the minimum on time of the pulse width modulator. Bootstrap pin for the high-side driver. A 100-nF capacitor is connected from this pin to SW and provides BOOT 18 I power to the high-side driver when the high-side FET is turned on. Clock and phase timing output while the device is configured as a clock master. In clock slave mode, the CLKIO 19 I/O master CLKIO pin is connected to the slave CLKIO pin to provide time base information to the slave. Power good output. This open drain output pulls low when the device is in any state other than in normal PGOOD 20 O regulation. Active soft-start, UVLO, overcurrent, undervoltage, overvoltage or overtemperature warning (115 °C junction) causes this output to pull low. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TPS40180 |
Similar Part No. - TPS40180RGET |
|
Similar Description - TPS40180RGET |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
