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W19B160BTAM7H Datasheet(PDF) 10 Page - Winbond |
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W19B160BTAM7H Datasheet(HTML) 10 Page - Winbond |
10 / 48 page W19B160BT/B DATA SHEET - 10 - held at VIH, but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. When the device is deselected during erasing or programming, the device initiates active current until the operation is completed. 6.1.6 Automatic Sleep Mode The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is independent from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when addresses are changed. In sleep mode, output data is latched and always available to the system. 6.1.7 #RESET: Hardware Reset Pin The #RESET pin provides a hardware method to reset the device to reading array data. When the #RESET pin is set to low for at least a period of tRP, the device will immediately terminate every operations in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data mode. To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. Current is reduced for the duration of the #RESET pulse. When #RESET is held at Vss ± 0.3V, the device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within Vss ± 0.3V, the standby current will be greater. The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the device, enabling the system to read the boot-up firmware from the device. If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until the internal reset operation is complete. If #RESET is asserted when a program or erase operation is not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH. 6.1.8 Output Disable Mode When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high impedance state. 6.1.9 Auto-select Mode The auto select mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the auto select codes can also be accessed in-system through the command register. When using programming equipment , the auto select mode requires VID (8.5 V to 11.5 V) on address pins A9. Address pins A6, A1, and A0 must be as shown in auto select table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. |
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