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LPC2214FBD144 Datasheet(PDF) 10 Page - NXP Semiconductors |
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LPC2214FBD144 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 45 page LPC2212_2214_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 3 January 2008 10 of 45 NXP Semiconductors LPC2212/2214 16/32-bit ARM microcontrollers P3[3]/A3 81 O External memory address line 3. P3[4]/A4 80 O External memory address line 4. P3[5]/A5 74 O External memory address line 5. P3[6]/A6 73 O External memory address line 6. P3[7]/A7 72 O External memory address line 7. P3[8]/A8 71 O External memory address line 8. P3[9]/A9 66 O External memory address line 9. P3[10]/A10 65 O External memory address line 10. P3[11]/A11 64 O External memory address line 11. P3[12]/A12 63 O External memory address line 12. P3[13]/A13 62 O External memory address line 13. P3[14]/A14 56 O External memory address line 14. P3[15]/A15 55 O External memory address line 15. P3[16]/A16 53 O External memory address line 16. P3[17]/A17 48 O External memory address line 17. P3[18]/A18 47 O External memory address line 18. P3[19]/A19 46 O External memory address line 19. P3[20]/A20 45 O External memory address line 20. P3[21]/A21 44 O External memory address line 21. P3[22]/A22 41 O External memory address line 22. P3[23]/A23/XCLK 40 O A23 — External memory address line 23. O XCLK — Clock output. P3[24]/CS3 36 O LOW-active Chip Select 3 signal. (Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF) P3[25]/CS2 35 O LOW-active Chip Select 2 signal. (Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF) P3[26]/CS1 30 O LOW-active Chip Select 1 signal. (Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF) P3[27]/WE 29 O LOW-active Write enable signal. P3[28]/BLS3/AIN7 28 O BLS3 — LOW-active Byte Lane Select signal (Bank 3). I AIN7 — ADC, input 7. This analog input is always connected to its pin. P3[29]/BLS2/AIN6 27 O BLS2 — LOW-active Byte Lane Select signal (Bank 2). I AIN6 — ADC, input 6. This analog input is always connected to its pin. P3[30]/BLS1 97 O LOW-active Byte Lane Select signal (Bank 1). P3[31]/BLS0 96 O LOW-active Byte Lane Select signal (Bank 0). n.c. 22 Pin not connected. RESET 135 I external reset input; a LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 142 I input to the oscillator circuit and internal clock generator circuits. XTAL2 141 O output from the oscillator amplifier. Table 3. Pin description …continued Symbol Pin Type Description |
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