P82B96TD datasheet(4/26 Pages) PHILIPS

Part #	P82B96TD

Description	Dual bidirectional bus buffer

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Manufacturer	PHILIPS [NXP Semiconductors]

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P82B96_6

Product data sheet

Rev. 06 — 31 January 2008

4 of 28

NXP Semiconductors

P82B96

Dual bidirectional bus buffer

7.

Functional description

Refer to Figure 1 “Block diagram of P82B96”.

The P82B96 has two identical buffers allowing buffering of both of the I2C-bus (SDA and

SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the

I2C-bus interface pin which drives the buffered bus, and a reverse signal path from the

buffered bus input to drive the I2C-bus interface. Thus these paths are:

• sense the voltage state of the I2C-bus pin Sx (or Sy) and transmit this state to the pin

Tx (Ty respectively), and

• sense the state of the pin Rx (Ry) and pull the I2C-bus pin LOW whenever Rx (Ry) is

LOW.

The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is

identical.

The I2C-bus pin (Sx) is designed to interface with a normal I2C-bus.

The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC.

The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is

3 mA.

The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic

LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC (with a typical switching

threshold of half VCC).

Tx is an open-collector output without ESD protection diodes to VCC. It may be connected

via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not

exceeded. It has a larger current sinking capability than a normal I2C-bus device, being

able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down

capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I2C-bus pin (Sx) is below

0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in

accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low

enough to be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically

0.8 V.

If the supply voltage VCC fails, then neither the I2C-bus nor the Tx output will be held LOW.

Their open-collector conﬁguration allows them to be pulled up to the rated maximum of

15 V even without VCC present. The input conﬁguration on Sx and Rx also present no

loading of external signals even when VCC is not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise times,

is less than 7 pF for all bus voltages and supply voltages including VCC =0V.

Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design

does not support this conﬁguration. Bidirectional I2C-bus signals do not allow any

direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy

to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the Rx/Ry of a P82B96

will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this

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