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S-1172B10-U5T1G Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-1172B10-U5T1G Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 34 page HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR Rev.1.1_00 S-1172 Series Seiko Instruments Inc. 11 Standard Circuit CIN *1 CL *2 Input Output GND Single GND VOUT VIN VSS ON/OFF *1. CIN is a capacitor for stabilizing the input. *2. Ceramic capacitor of 4.7 µF or more can be used as CL. Figure 11 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Application Conditions Input capacitor (CIN) : 4.7 µF or more Output capacitor (CL) : 4.7 µF or more (ceramic capacitor) Caution 1. Set input capacitor (CIN) and output capacitor (CL) as CIN = CL. 2. Generally, series regulator may oscillate depending on the external components. Confirm that no oscillation occurs in the application for which the above capacitors are used. Selection of Input and Output Capacitors (CIN, CL) The S-1172 Series requires an output capacitor between the VOUT and VSS pin for phase compensation. Operation is stabilized by a ceramic capacitor with an output capacitance of 4.7 µF or more over the entire temperature range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 4.7 µF or more. The values of output overshoot and undershoot, which are transient response characteristics, vary depending on the value of output capacitor. The required value of capacitance for the input capacitor differs depending on the application. Set the value for input capacitor (CIN) and output capacitor (CL) as follows. CIN ≥ 4.7 µF CL ≥ 4.7 µF CIN = CL Caution The S-1172 Series may oscillate if setting the value as CIN ≥ 4.7 µF, CL ≥ 4.7 µF, CIN < CL. Define the values by sufficient evaluation including the temperature characteristics under the usage condition. |
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