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S-1165B50MC-N7JTFG Datasheet(PDF) 9 Page - Seiko Instruments Inc |
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S-1165B50MC-N7JTFG Datasheet(HTML) 9 Page - Seiko Instruments Inc |
9 / 23 page HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.3.1_00 S-1165 Series Seiko Instruments Inc. 9 Standard Circuit ON/OFF VSS VOUT VIN CIN *1 CL *2 Input Output GND Single GND *1. CIN is a capacitor for stabilizing the input. *2. A tantalum capacitor (2.2 μF or more) can be used. Figure 9 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Application Conditions Input capacitor (CIN): 1.0 μF or more Output capacitor (CL): 2.2 μF or more (tantalum capacitor) Caution A general series regulator may oscillate, depending on the external components selected. Check that no oscillation occurs with the application using the above capacitor. |
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