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S-8120CNB-DRB-TF-G Datasheet(PDF) 10 Page - Seiko Instruments Inc |
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S-8120CNB-DRB-TF-G Datasheet(HTML) 10 Page - Seiko Instruments Inc |
10 / 21 page CMOS TEMPERATURE SENSOR IC S-8110C/8120C Series Rev.4.3_00 Seiko Instruments Inc. 10 Precautions • Wiring patterns for VDD pin, VOUT pin and VSS pin should be designed to hold low impedance. • In this IC, if load capacitance of VOUT pin is large, VOUT pin voltage may oscillate. It is recommended not to use the external capacitor between the VOUT and VSS pin. In case of using external capacitor, mount it near the VOUT pin. When connecting A/D converter etc. to the VOUT pin, input pin capacitance of A/D converter and the parasitic capacitance component between wires are included as load capacitance. To prevent oscillation, it is recommended to use the following output load condition. Load capacitance of VOUT pin (CL) : 100 pF or less • In this IC, if load resistance of VOUT pin is small, VOUT pin voltage may oscillate. It is recommended not to use the external resistor between the VOUT and VSS pin. When connecting A/D converter etc. to the VOUT pin, input resistance of A/D converter and the parasitic resistance component between wires are included as load resistance. To prevent oscillation, it is recommended to use the following output load condition. Load resistance of VOUT pin (RL) : 500 kΩ or more VSS VDD VOUT S-8110C/8120C Series CL RL VOUT Figure 9 Caution The above connection diagram and constant will not guarantee successful operation. Perform through evaluation using the actual application to set the constant. • Please do not connect a pull-up resistor to the output voltage pin. • The application condition for input voltage, output voltage and load current must not exceed the package power dissipation. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • In determining output current, attention should be paid to the output current value specified in the Table 5 to Table 6 for electrical characteristics and the footnote *1 of the Table 5 to Table 6. • SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party. |
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