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ICS841S02BGIT Datasheet(PDF) 3 Page - Integrated Device Technology |
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ICS841S02BGIT Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 17 page IDT™ / ICS™ PCI EXPRESS CLOCK GENERATOR 3 ICS841S02BGI REV. C NOVEMBER 1, 2007 ICS841S02I PCI EXPRESS™ CLOCK GENERATOR PRELIMINARY To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are nor- mally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. SERIAL DATA INTERFACE The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in se- quential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the sys- tem controller can access individually indexed bytes. The off- set of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). DATA PROTOCOL TABLE 3A. COMMAND CODE DEFINITION T I Bn o i t p i r c s e D 7 . n o i t a r e p o e t i r w e t y b r o d a e r e t y B = 1 , n o i t a r e p o e t i r w k c o l b r o d a e r k c o l B = 0 5 : 6. e c i v e d s s e c c a o t " 0 0 " o t t e s , s s e r d d a t c e l e s p i h C 0 : 4 e b t s u m s t i b e s e h t , s n o i t a r e p o e t i r w k c o l b r o d a e r k c o l b r o F . n o i t a r e p o e t i r w e t y b r o d a e r e t y b r o f t e s f f o e t y B . " 0 0 0 0 0 " TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL T I Be t i r W k c o l B = n o i t p i r c s e DT I Bd a e R k c o l B = n o i t p i r c s e D 1t r a t S1 t r a t S 8 : 2s t i b 7 - s s e r d d a e v a l S8 : 2s t i b 7 - s s e r d d a e v a l S 9e t i r W9 e t i r W 0 1e v a l s m o r f e g d e l w o n k c A0 1e v a l s m o r f e g d e l w o n k c A 8 1 : 1 1s t i b 8 - e d o C d n a m m o C8 1 : 1 1s t i b 8 - e d o C d n a m m o C 9 1e v a l s m o r f e g d e l w o n k c A9 1e v a l s m o r f e g d e l w o n k c A 7 2 : 0 2s t i b 8 - t n u o C e t y B0 2t r a t s t a e p e R 8 2e v a l s m o r f e g d e l w o n k c A7 2 : 1 2s t i b 7 - s s e r d d a e v a l S 6 3 : 9 2s t i b 8 - 1 e t y b a t a D8 21 = d a e R 7 3e v a l s m o r f e g d e l w o n k c A9 2e v a l s m o r f e g d e l w o n k c A 5 4 : 8 3s t i b 8 - 2 e t y b a t a D7 3 : 0 3s t i b 8 - e v a l s m o r f t n u o C e t y B 6 4e v a l s m o r f e g d e l w o n k c A8 3e g d e l w o n k c A s e g d e l w o n k c A e v a l S / e t y B a t a D6 4 : 9 3s t i b 8 - e v a l s m o r f 1 e t y B a t a D s t i b 8 - N e t y B a t a D7 4e g d e l w o n k c A e v a l s m o r f e g d e l w o n k c A5 5 : 8 4s t i b 8 - e v a l s m o r f 2 e t y B a t a D p o t S6 5e g d e l w o n k c A s e g d e l w o n k c A / e v a l S m o r f s e t y B a t a D s t i b 8 - e v a l s m o r f N e t y B a t a D e g d e l w o n k c A t o N |
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