HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

S-T111 Series

Seiko Instruments Inc.

8

Standard Circuit

ON/OFF

VSS

VOUT

VIN

*1

*2

Input

Output

GND

Single GND

*2. A ceramic capacitor of 0.1

μF or more can be used for C

Figure 9

Caution The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

Application Conditions

0.1

μF or more

0.1

μF or more

ESR of output capacitor:

10

Ω or less

Caution A general series regulator may oscillate, depending on the external components selected.

Check that no oscillation occurs with the application using the above capacitor.

The S-T111 Series requires an output capacitor between the VOUT and VSS pins for phase compensation.

Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1

μF or more in the entire

temperature range.

However, when using an OS capacitor, tantalum capacitor, or aluminum electrolytic

capacitor, a ceramic capacitor with a capacitance of 0.1

μF or more and an ESR of 10 Ω or less is required.

The value of the output overshoot or undershoot transient response varies depending on the value of the output

capacitor. The required capacitance of the input capacitor differs depending on the application.

The recommended value for an application is 1.0

μF or more for C

when selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature

characteristics, on the actual device.