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S-L2980A56MC-TF-G Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-L2980A56MC-TF-G Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 23 page HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.4.1_00 S-L2980 Series Seiko Instruments Inc. 11 Operation 1. Basic Operation Figure 11 shows the block diagram of the S-L2980 Series. The error amplifier compares the reference voltage (Vref) with the Vfb, which is the output voltage resistance-divided by the feedback resistors Rs and Rf. It supplies the output transistor with the gate voltage necessary to ensure certain output voltage free of any fluctuations of input voltage and temperature. Reference voltage circuit VOUT *1 VSS VIN Rs Rf Error amplifier Current source Vref – + Vfb *1. Parasitic diode Figure 11 2. Output Transistor The S-L2980 Series uses a low on-resistance P-channel MOS FET as the output transistor. Be sure that VOUT does not exceed VIN+0.3 V to prevent the voltage regulator from being broken due to inverse current flowing from VOUT pin through a parasitic diode to VIN pin. |
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