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SN65LVCP23PW Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVCP23PW Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 19 page  www.ti.com SWITCHING CHARACTERISTICS PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL1 SEL0 IN0+ IN0- VCC IN1+ IN1- VCC EN0 EN1 OUT0+ OUT0- GND OUT1+ OUT1- GND D or PW PACKAGE (TOP VIEW) SN65LVCP23 SLLS554E – NOVEMBER 2002 – REVISED MAY 2006 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSET Input to SEL setup time Figure 5 1 0.5 ns tHOLD Input to SEL hold time Figure 5 1.1 0.5 ns tSWITCH SEL to switched output Figure 5 1.7 2.5 ns tPHKL Disable time, high-level-to-known LOW Figure 4 2 2.5 ns tPKLH Enable time, known LOW-to-high-level output Figure 4 2 2.5 ns tLHT Differential output signal rise time (20% – 80%)(1) Figure 3 80 110 220 ps tHLT Differential output signal fall time (20% – 80%)(1) Figure 3 80 110 220 ps VID = 200 mV, 50% duty cycle, VCM = 1.2 V, 15 30 ps 650 MHz tJIT Added peak-to-peak jitter VID = 200 mV, PRBS = 223–1 data pattern and K28.5 (0011111010), 50 100 ps VCM = 1.2 V at 1.3 Gbps VID = 200 mV, 50% duty cycle, tJrms Added random jitter (rms) 0.3 0.5 psRMS VCM = 1.2 V, 650 MHz tPLHD Propagation delay time, low-to-high-level output(1) VCC = 3.3 V, TA = 25°C, See Figure 3 400 750 1100 ps tPHLD Propagation delay time, high-to-low-level output(1) VCC = 3.3 V, TA = 25°C, See Figure 3 400 750 1100 ps tskew Pulse skew (|tPLHD– tPHLD|)(2) Figure 3 20 100 ps tCCS Output channel-to-channel skew, splitter mode Figure 3 10 50 ps fMAX Maximum operating frequency(3) 1 GHz (1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps (2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device. (3) Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD ≥ 300 mV. 7 Submit Documentation Feedback |
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