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ICS840002AGI-01 Datasheet(PDF) 9 Page - Integrated Device Technology |
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ICS840002AGI-01 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 13 page 840002AGI-01 www.icst.com/products/hiperclocks.html REV. A OCTOBER 18, 2007 9 ICS840002I-01 FEMTOCLOCKS™ CRYSTAL-TO- LVCMOS/LVTTL FREQUENCY SYNTHESIZER www.IDT.com LAYOUT GUIDELINE Figure 3 shows a schematic example of the ICS840002I-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 25MHz crystal is used. The C1=22pF and FIGURE 3. ICS840002I-01 SCHEMATIC EXAMPLE C2=22pF are recommended for frequency accuracy. For differ- ent board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K Ω pullup or pulldown resis- tors can be used for the logic control input pins. RU2 Not Install Logic Control Input Examples C6 0.1u Set Logic Input to '1' RD2 1K VDD Zo = 50 Ohm XTAL2 VDD C3 10uF X1 To Logic Input pins VDD R1 10 XTAL1 Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. VDD VDD R4 100 LVCMOS Set Logic Input to '0' C4 0.01u R2 33 Zo = 50 Ohm VDDA RU1 1K U1 ICS840002I-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD XTAL_OUT XTAL_IN VDDO Q1 Q0 GND GND FSEL1 LVCMOS If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. To Logic Input pins RD1 Not Install C5 0.1u R3 100 C1 22pF C2 22pF Optional Termination |
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