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843002AKI-40 Datasheet(PDF) 10 Page - Integrated Device Technology |
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843002AKI-40 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 23 page  ICS843002I-40 175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 10 ICS843002AKI-40 REV. A NOVEMBER 7, 2007 Output Duty Cycle/Pulse Width/Period Application Information Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from CLKx to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. t PW t PERIOD t PW t PERIOD odc = x 100% nQA, nQB QA, QB |
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