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ICS844246BGILF Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS844246BGILF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 16 page IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 10 ICS844246BGI REV. A NOVEMBER 14, 2007 ICS844246I FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PRELIMINARY LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50 Ω. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE XTAL_IN XTAL_OUT VCC R2 Ro R1 Zo = 50 Rs VCC .1uf VDD VDD Zo = Ro + Rs Reference Document: JEDEC Publication 95, MO-153 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 Ω differential transmission line environment, LVDS dr ivers FIGURE 4. TYPICAL LVDS DRIVER TERMINATION require a matched load termination of 100 Ω across near the receiver input. 2.5V or 3.3V + - VDD 100 Ohm Differential Transmission Line R1 100 LVDS_Driv er |
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