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ICS853017AM Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS853017AM Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 15 page IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER 8 ICS853017AM REV. B OCTOBER 24, 2007 ICS853017 QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER PRELIMINARY LVPECL CLOCK INPUT INTERFACE The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and V OH must meet the V PP and V CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V R2 50 R1 50 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm PCLK/nPCLK 2.5V Zo = 60 Ohm SSTL HiPerClockS PCLK nPCLK R2 120 3.3V R3 120 Zo = 60 Ohm R1 120 R4 120 2.5V FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V R5 100 - 200 3.3V 3.3V HiPerClockS PCLK nPCLK R1 125 PCLK/nPCLK R2 125 R3 84 C1 C2 Zo = 50 Ohm R4 84 Zo = 50 Ohm R6 100 - 200 3.3V LVPECL 3.3V HiPerClockS PCLK nPCLK R2 84 R3 125 Input Zo = 50 Ohm R4 125 R1 84 LVPECL 3.3V 3.3V Zo = 50 Ohm C2 R2 1K R5 100 Zo = 50 Ohm 3.3V 3.3V C1 R3 1K LVDS R4 1K HiPerClockS PCLK nPCLK R1 1K Zo = 50 Ohm 3.3V PC L K /n PC LK |
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